1. Field of the Invention
The present invention relates to a digital data transmission system and, more particularly, to a method of transmitting a frame pulse signal in parallel with data principally within a device in a communication system using frames, packets, and the like.
2. Description of the Background Art
For frame synchronization, conventional frame synchronization type digital data communication systems have employed two methods: a first method wherein a transmitter transmits data in which a frame pattern is embedded and a receiver detects a frame pulse signal from the data, and a second method wherein a transmitter transmits a frame pulse signal in parallel with data.
In general, the first method is employed for data transmission between devices, and the second method is employed for data transmission within a device. In some cases, for bit synchronization with data to be received, the receiver comprises a clock recovery circuit and the transmitter also transmits a clock in parallel with data.
FIG. 31 is a block diagram showing the transmission of a frame pulse signal and a clock in parallel with digital data. As shown, a transmitting portion 39 transmits data DA, a frame pulse signal FP, and a clock CK from drivers 33 to 35 provided therein through transmission lines 51 to 53 respectively to a receiving portion 49. In FIG. 31, the reference numerals 31 and 32 designate flip-flops for processing the data DA and the frame pulse signal FP. The transmission lines 51 to 53 are formed by wires, cables, printed wiring, and the like.
The receiving portion 49 comprises drivers 43 to 45 for receiving the data DA, the frame pulse signal FP, and the clock CK through the transmission lines 51 to 53, and flip-flops 41 and 42 operating in synchronism with the clock CK for performing signal processing based on the data DA and the frame pulse signal FP. Examples of the clock CK, the frame pulse signal FP and the data DA are shown in FIG. 32.
The receiving portion 49 is provided for each board corresponding to one or more transmitting LSI circuits of a transmitter.
The digital data transmission system which contains a plurality of lines like a switching system in the above described manner to transmit the data, the frame pulse signal, and the clock in parallel in opposite directions for each line is disadvantageous in that the number of input/output pins of an interface LSI circuit or the number of input/output connectors of a board limit the number of lines to be contained in the digital data transmission system.
FIG. 33 illustrates the connection between N interface LSI circuits 61 to 6N (where N is a natural number) and a single Nxc3x97N switch LSI circuit 60. As shown, since each of the interface LSI circuits 61 to 6N has six pins for transmitting and receiving the data DA, the frame pulse signal FP, and the clock CK, the switch LSI circuit 60 needs 6xc2x7N input/output pins. The interface LSI circuits 61 to 6N comprise 3-bit output buffer groups G21 to G2N, and 3-bit input buffer groups G31 to G3N, respectively. The switch LSI circuit 60 comprises 3bit output buffer groups G41 to G4N, and 3-bit input buffer groups G51 to G5N.
M-bit parallel transmission/reception of the data DA requires 2(2+M) input/output pins in each of the interface LSI circuits and accordingly requires 2(2+M)xc2x7N pins in the switch LSI circuit 60. Since the switch LSI circuit 60 requires additional pins for a control signal, the number of lines to be contained in the digital data transmission system (the number of connectable interface LSI circuits) is limited due to the shortage of pins.
The conventional digital data transmission system constructed as above described has required a great number of signal lines when the system must transmit the digital data, the frame pulse signal, and the clock.
Additionally, the frame pulse signal has been multiplexed with the digital data heretofore. However, because of the irregularity of the digital data, much time and high costs are required for the multiplexing of signals in a transmitter and the separation of the signals in a receiver.
A first aspect of the present invention is intended for a digital data transmission system for transmitting digital data in a frame synchronization manner. According to the present invention, the digital data transmission system comprises a transmitting portion for transmitting digital data, and a receiving portion for receiving the digital data, the transmitting portion comprising a clock multiplexing circuit for multiplexing a frame pulse signal for frame synchronization with a clock having a predetermined period to output a multiple clock to the receiving portion, the receiving portion comprising a clock recovery circuit for reproducing the clock from the multiple clock to provide a recovered clock by using a synchronization loop circuit for synchronizing a reference signal associated with the multiple clock and a comparison output signal, and a frame pulse signal separation circuit for separating the frame pulse signal from the multiple clock to provide a recovered frame pulse signal by using the recovered clock.
Preferably, according to a second aspect of the present invention, in the digital data transmission system of the first aspect, the clock multiplexing circuit includes clock shaping means receiving the clock and the frame pulse signal, the clock shaping means for performing a shaping process of masking the clock at a fixed value at least for the predetermined period during the time the frame pulse signal is active, the clock shaping means for outputting the clock intactly as the multiple clock for other time periods.
Preferably, according to a third aspect of the present invention, in the digital data transmission system of the second aspect, the clock shaping means further receives an enable signal and includes enabling means for disabling the shaping process to force the clock to be outputted intactly as the multiple clock when the enable signal is inactive.
Preferably, according to a fourth aspect of the present invention, in the digital data transmission system of the second aspect, the clock recovery circuit includes: phase comparing means for making a comparison between the phase of the multiple clock and the phase of the recovered clock, control signal output means for outputting a control signal on the basis of a result of the phase comparison of the phase comparing means, and oscillating means for generating the recovered clock at an oscillation frequency based on the control signal, the phase comparing means, the control signal output means, and the oscillating means constituting a PLL circuit for performing a phase synchronization process on the multiple clock and the recovered clock, the synchronization loop circuit including the PLL circuit, the reference signal including the multiple clock, the comparison output signal including the recovered clock.
Preferably, according to a fifth aspect of the present invention, in the digital data transmission system of the fourth aspect, the clock recovery circuit further includes masking means receiving the recovered frame pulse signal, the masking means for disabling the phase synchronization when the recovered frame pulse signal indicates an active state.
Preferably, according to a sixth aspect of the present invention, in the digital data transmission system of the fourth aspect, the clock recovery circuit further includes synchronization detecting means for detecting whether or not the multiple clock and the recovered clock is in synchronism with each other to disable the phase synchronization process upon detection of synchronization.
Preferably, according to a seventh aspect of the present invention, in the digital data transmission system of the second aspect, the clock recovery circuit includes: phase comparing means for making a comparison between the phase of the multiple clock and the phase of a delayed multiple clock, control signal output means for outputting a control signal on the basis of a result of the phase comparison of the phase comparing means, and variable delay means for providing a time delay of n times the predetermined period (where n is a natural number) to the multiple clock on the basis of the control signal to output the delayed multiple clock, the phase comparing means, the control signal output means, and the variable delay means constituting a DLL circuit for performing a delay synchronization process on the multiple clock and the delayed multiple clock, the synchronization loop circuit including the DLL circuit, the reference signal including the multiple clock, the comparison output signal including the delayed multiple clock, and the clock recovery circuit further includes logical OR means for ORing the multiple clock and the delayed multiple clock to output the recovered clock.
Preferably, according to an eighth aspect of the present invention, in the digital data transmission system of the second aspect, the clock recovery circuit includes: phase comparing means for making a comparison between the phase of a system clock independent of the multiple clock and the phase of an oscillation signal, control signal output means for outputting a control signal on the basis of a result of the phase comparison of the phase comparing means, oscillating means for generating the oscillation signal at an oscillation frequency based on the control signal, and variable delay means for providing a time delay of the predetermined period to the multiple clock on the basis of the control signal to output a delayed multiple clock, the phase comparing means, the control signal output means, and the oscillating means constituting a PLL circuit for performing a phase synchronization process on the system clock and the oscillation signal, the synchronization loop circuit including the PLL circuit, the reference signal including the system clock, the comparison output signal including the oscillation signal, and the clock recovery circuit further includes logical OR means for ORing the multiple clock and the delayed multiple clock to output the recovered clock.
Preferably, according to a ninth aspect of the present invention, in the digital data transmission system of the second aspect, the frame pulse signal separation circuit includes fixed value detecting means for detecting whether or not the multiple clock maintains the fixed value for the predetermined period to output the recovered frame pulse signal which is active when the multiple clock maintains the fixed value for the predetermined period and is inactive otherwise.
Preferably, according to a tenth aspect of the present invention, in the digital data transmission system of the first aspect, the clock multiplexing circuit includes clock shaping means receiving the clock and the frame pulse signal, the clock shaping means for performing a shaping process of doubling the predetermined period of the clock to output the multiple clock during the time the frame pulse signal is active.
Preferably, according to an eleventh aspect of the present invention, in the digital data transmission system of the tenth aspect, the clock recovery circuit includes: phase comparing means receiving the earliest and second earliest ones of the multiple clock, a first delayed multiple clock, and a second delayed multiple clock respectively as first and second comparison signals for making a comparison between the phases of the first and second comparison signals, control signal output means for outputting a control signal on the basis of a result of the phase comparison of the phase comparing means, first variable delay means for providing a time delay of n times the predetermined period (where n is a natural number) to the multiple clock on the basis of the control signal to output the first delayed multiple clock, and second variable delay means for providing a time delay of n times the predetermined period to the first delayed multiple clock on the basis of the control signal to output the second delayed multiple clock, the phase comparing means, the control signal output means, and at least one of the first and second variable delay means constituting a DLL circuit for performing a delay synchronization process on the first and second comparison signals, the synchronization loop circuit including the DLL circuit, the reference signal including the first comparison signal, the comparison output signal including the second comparison signal, and the clock recovery circuit further includes majority means for outputting at least two of three signal levels of the multiple clock, the first delayed multiple clock, and the second delayed multiple clock which are provided moment by moment as a signal level of the recovered clock.
Preferably, according to a twelfth aspect of the present invention, in the digital data transmission system of the tenth aspect, the clock recovery circuit includes: phase comparing means for making a comparison between the phase of a system clock independent of the multiple clock and the phase of an oscillation signal, control signal output means for outputting a control signal on the basis of a result of the phase comparison of the phase comparing means, oscillating means for generating the oscillation signal at an oscillation frequency based on the control signal, first variable delay means for providing a time delay of the predetermined period to the multiple clock on the basis of the control signal to output a first delayed multiple clock, and second variable delay means for providing a time delay of the predetermined period to the first delayed multiple clock on the basis of the control signal to output a second delayed multiple clock, the phase comparing means, the control signal output means, and the oscillating means constituting a PLL circuit for performing a phase synchronization process on the system clock and the oscillation signal, the synchronization loop circuit including the PLL circuit, the reference signal including the system clock, the comparison output signal including the oscillation signal, and the clock recovery circuit further includes majority means for outputting at least two of three signal levels of the multiple clock, the first delayed multiple clock, and the second delayed multiple clock which are provided moment by moment as a signal level of the recovered clock.
A thirteenth aspect of the present invention is intended for a digital data transmission system for transmitting digital data in a frame synchronization manner. According to the present invention, the digital data transmission system comprises first to Nth transmitting portions for transmitting digital data, and a receiving portion for receiving the digital data, the first to Nth transmitting portions comprising clock multiplexing circuits, respectively, for multiplexing first to Nth frame pulse signals for frame synchronization with first to Nth clocks having first to Nth periods to output first to Nth multiple clocks to the receiving portion, the receiving portion comprising: a clock recovery circuit for reproducing the first to Nth clocks from the first to Nth multiple clocks to provide first to Nth recovered clocks respectively by using a synchronization loop circuit for synchronizing a reference signal associated with the first multiple clock and a comparison output signal, and first to Nth frame pulse signal separation circuits for separating the first to Nth frame pulse signals from the first to Nth multiple clocks to provide first to Nth recovered frame pulse signals by using the first to Nth recovered clocks, respectively.
Preferably, according to a fourteenth aspect of the present invention, in the digital data transmission system of the thirteenth aspect, the clock recovery circuit has a synchronization detection function of detecting whether or not the synchronization loop circuit has synchronized the reference signal and the comparison output signal to output to the first transmitting portion a synchronization detection signal indicating whether the synchronization loop circuit is in a locked state in which the reference signal and the comparison output signal are synchronized or in an unlocked state in which the reference signal and the comparison output signal are not synchronized; and the clock multiplexing circuit of the first transmitting portion receives the synchronization detection signal, and has an enabling function of forcing the first clock to be outputted intactly as the first multiple clock when the synchronization detection signal indicates the unlocked state and of multiplexing the first frame pulse signal with the first clock to output the first multiple clock when the synchronization detection signal indicates the locked state.
Preferably, according to a fifteenth aspect of the present invention, in the digital data transmission system of the thirteenth aspect, the clock recovery circuit includes: phase comparing means for making a comparison between the phase of the first multiple clock and the phase of a first delayed multiple clock, control signal output means for outputting a control signal on the basis of a result of the phase comparison of the phase comparing means, first to Nth variable delay means for providing time delays of n times the first to Nth periods (where n is a natural number) to the first to Nth multiple clocks commonly on the basis of the control signal to output first to Nth delayed multiple clocks respectively, and first to Nth logical OR means for ORing the first to Nth multiple clocks and the first to Nth delayed multiple clocks to output the first to Nth recovered clocks respectively, the phase comparing means, the control signal output means, and the first variable delay means constituting a DLL circuit for performing a delay synchronization process on the first multiple clock and the first delayed multiple clock, the synchronization loop circuit including the DLL circuit, the reference signal including the first multiple clock, the comparison output signal including the first delayed multiple clock.
Preferably, according to a sixteenth aspect of the present invention, in the digital data transmission system of the thirteenth aspect, the clock recovery circuit includes: phase comparing means for making a comparison between the phase of a system clock independent of the first to Nth multiple clocks and the phase of an oscillation signal, control signal output means for outputting a control signal on the basis of a result of the phase comparison of the phase comparing means, oscillating means for generating the oscillation signal at an oscillation frequency based on the control signal, first to Nth variable delay means for providing time delays of the first to Nth periods to the first to Nth multiple clocks commonly on the basis of the control signal to output first to Nth delayed multiple clocks respectively, and first to Nth logical OR means for ORing the first to Nth multiple clocks and the first to Nth delayed multiple clocks to output the first to Nth recovered clocks respectively, the phase comparing means, the control signal output means, and the oscillating means constituting a PLL circuit for performing a phase synchronization process on the system clock and the oscillation signal, the synchronization loop circuit including the PLL circuit, the reference signal including the system clock, the comparison output signal including the oscillation signal.
Preferably, according to a seventeenth aspect of the present invention, in the digital data transmission system of the thirteenth aspect, the ith frame pulse signal separation circuit (i=1 to N) includes fixed value detecting means for detecting whether or not the ith multiple clock maintains a fixed value for the ith period to output the ith recovered frame pulse signal which is active when the ith multiple clock maintains the fixed value for the ith period and is inactive otherwise.
An eighteenth aspect of the present invention is intended for a digital data transmission system for transmitting digital data in a frame synchronization manner. According to the present invention, the digital data transmission system comprises first and second transmitting and receiving portions for transmitting digital data and for receiving digital data, the first transmitting and receiving portion comprising a first clock multiplexing circuit for multiplexing a first frame pulse signal for frame synchronization with a first clock having a predetermined period to output a first multiple clock to the second transmitting and receiving portion, the second transmitting and receiving portion comprising a second clock multiplexing circuit for multiplexing a second frame pulse signal for frame synchronization with a second clock having the predetermined period to output a second multiple clock to the first transmitting and receiving portion, the first transmitting and receiving portion further comprising: a first clock recovery circuit for reproducing the second clock as a first recovered clock from the second multiple clock to provide the first recovered clock by using a first synchronization loop circuit for synchronizing a first reference signal associated with the second multiple clock and a first comparison output signal, the first clock recovery circuit having a synchronization detection function of detecting whether or not the first reference signal and the first comparison output signal have been synchronized to output a first synchronization detection signal indicating whether the first synchronization loop circuit is in a locked state in which the first reference signal and the first comparison output signal are synchronized or in an unlocked state in which the first reference signal and the first comparison output signal are not synchronized, and a first frame pulse signal separation circuit for separating the second frame pulse signal as a first recovered frame pulse signal from the second multiple clock to provide the first recovered frame pulse signal by using the first recovered clock, the second transmitting and receiving portion further comprising: a second clock recovery circuit for reproducing the first clock as a second recovered clock from the first multiple clock to provide the second recovered clock by using a second synchronization loop circuit for synchronizing a second reference signal associated with the first multiple clock and a second comparison output signal, the second clock recovery circuit having a synchronization detection function of detecting whether or not the second reference signal and the second comparison output signal have been synchronized to output a second synchronization detection signal indicating whether the second synchronization loop circuit is in a locked state in which the second reference signal and the second comparison output signal are synchronized or in an unlocked state in which the second reference signal and the second comparison output signal are not synchronized, and a second frame pulse signal separation circuit for separating the first frame pulse signal as a second recovered frame pulse signal from the first multiple clock to provide the second recovered frame pulse signal by using the second recovered clock, wherein the first clock multiplexing circuit of the first transmitting and receiving portion receives the first synchronization detection signal, and has an enabling function of forcing the first clock to be outputted intactly as the first multiple clock when the first synchronization detection signal indicates the unlocked state and of multiplexing the first frame pulse signal with the first clock to output the first multiple clock when the first synchronization detection signal indicates the locked state, and wherein the second clock multiplexing circuit of the second transmitting and receiving portion receives the second synchronization detection signal, and has an enabling function of forcing the second clock to be outputted intactly as the second multiple clock when the second synchronization detection signal indicates the unlocked state and of multiplexing the second frame pulse signal with the second clock to output the second multiple clock when the second synchronization detection signal indicates the locked state.
As above described, in the digital data transmission system in accordance with the first aspect of the present invention, the transmitting portion employs the clock multiplexing circuit to multiplex the frame pulse signal for frame synchronization with the clock having the predetermined period to output the multiple clock to the receiving portion, and the receiving portion employs the clock recovery circuit and the frame pulse signal separation circuit to reproduce the clock and the frame pulse signal from the multiple clock to provide the recovered clock and the recovered frame pulse signal.
Thus, two signal lines which have been required to transmit the frame pulse signal and the clock are reduced to one signal line for transmitting the multiple clock. Further, since the clock is a signal having regularly repeated high and low levels during the predetermined period, the clock multiplexing circuit, the clock recovery circuit and the frame pulse signal separation circuit may be of relatively simple circuit construction.
The clock shaping means of the clock multiplexing circuit in accordance with the second aspect of the present invention performs the shaping process of masking the clock at the fixed value at least for the predetermined period during the time the frame pulse signal is active, and outputs the clock intactly as the multiple clock for other time periods.
Therefore, the clock shaping means may be relatively readily constructed using a latch for storing the frame pulse signal in response to the high and low levels of the clock, and a simple logic gate for logic operation which outputs the fixed value when the output from the latch indicates that the frame pulse signal is active and which outputs the clock intactly when the output from the latch indicates that the frame pulse signal is inactive.
The clock shaping means in accordance with the third aspect of the present invention includes the enabling means for disabling the shaping process to force the clock to be outputted intactly as the multiple clock when the enable signal is inactive. The clock may be outputted intactly as the multiple clock as required.
The clock recovery circuit in accordance with the fourth aspect of the present invention supplies as the recovered clock the comparison output signal from the PLL circuit which performs the phase synchronization process on the multiple clock and the comparison output signal. Thus, the clock recovery circuit may be of a relatively simple circuit construction comprised of only the PLL circuit.
The masking means of the clock recovery circuit in accordance with the fifth aspect of the present invention disables the phase synchronization process of the PLL circuit when the recovered frame pulse signal indicates the active state, thereby preventing the malfunctions of the phase synchronization process at a position of the multiple clock where the frame pulse signal which is active is multiplexed.
The synchronization detecting means of the clock recovery circuit in accordance with the sixth aspect of the present invention disables the phase synchronization process upon detection of the synchronization of the multiple clock and recovered clock. Thus, the stable recovered clock may be provided after the synchronization detection.
The clock recovery circuit in accordance with the seventh aspect of the present invention comprises the DLL circuit for performing the delay synchronization process on the multiple clock and the delayed multiple clock, and the logical OR means for ORing the multiple clock and the delayed multiple clock to output the recovered clock.
The clock recovery circuit in accordance with the seventh aspect of the present invention which employs the DLL circuit may to reduce the time required for synchronization to provide the recovered clock at an early stage. Further, since the variable delay element should provide the time delay of n times the period of the clock, the range of the frequency of the clock for synchronization is widely extended.
The clock recovery circuit in accordance with the eighth aspect of the present invention comprises the PLL circuit for performing the phase synchronization process on the system clock and the oscillation signal, and the logical OR means for ORing the multiple clock and the delayed multiple clock to output the recovered clock.
Since the system clock serving as the reference signal is independent of the multiple clock and is not multiplexed with the frame pulse signal, the PLL circuit in accordance with the eighth aspect of the present invention may perform the phase synchronization process without malfunctions, and the logical OR means may provide the highly stable recovered clock at an early stage.
The fixed value detecting means of the frame pulse signal separation circuit in accordance with the ninth aspect of the present invention outputs the recovered frame pulse signal which is active when the multiple clock maintains the fixed value for the predetermined period.
Therefore, the fixed value detecting means may be of a relatively simple construction by employing latch means for latching the value of the multiple clock when the clock does not have the fixed value for each predetermined period on the basis of the regularity of the recovered clock and the clock.
The clock shaping means of the clock multiplexing circuit in accordance with the tenth aspect of the present invention performs the shaping process of doubling the predetermined period of the clock to output the multiple clock during the time the frame pulse signal is active. The multiplexing of the frame pulse signal allows the production of the multiple clock having a good DC balance.
The clock recovery circuit in accordance with the eleventh aspect of the present invention comprises the DLL circuit for performing the delay synchronization process on the first and second comparison signals which are two of the multiple clock, the first delayed multiple clock and the second delayed multiple clock, and the majority means for outputting at least two of the three signal levels of the multiple clock, the first delayed multiple clock and the second delayed multiple clock which are provided moment by moment as the signal level of the recovered clock.
Thus, the clock recovery circuit in accordance with the eleventh aspect of the present invention which employs the DLL circuit may reduce the time required for synchronization to provide the recovered clock from the output of the majority means at an early stage. Further, since the variable delay element should provide the time delay of n times the period of the clock, the range of the frequency of the clock for synchronization is widely extended.
The clock recovery circuit in accordance with the twelfth aspect of the present invention comprises the PLL circuit for performing the phase synchronization process on the system clock and the oscillation signal, and the majority means for outputting at least two of the three signal levels of the multiple clock, the first delayed multiple clock and the second delayed multiple clock which are provided moment by moment as the signal level of the recovered clock.
Since the system clock serving as the reference signal is independent of the multiple clock and is not multiplexed with the frame pulse signal, the PLL circuit in accordance with the twelfth aspect of the present invention may perform the phase synchronization process without malfunctions, and the majority means may provide the highly stable recovered clock at an early stage.
In the digital data transmission system in accordance with the thirteenth aspect of the present invention, the clock recovery circuit provides the first to Nth recovered clocks from the first to Nth multiple clocks by using the synchronization loop circuit for synchronizing the reference signal associated with the first multiple clock and the comparison output signal. The supply of the N recovered clocks from the single synchronization loop circuit allows the significant reductions in circuit size and power consumption.
The clock multiplexing circuit of the first transmitting portion in accordance with the fourteenth aspect of the present invention forces the first clock to be outputted intactly as the first multiple clock when the synchronization detection signal from the receiving portion indicates the unlocked state, and multiplexes the first frame pulse signal with the first clock to output the first multiple clock when the synchronization detection signal indicates the locked state.
Thus, the clock recovery circuit of the receiving portion may receive the first clock as the first multiple clock until the synchronization loop circuit is locked. The clock recovery circuit may be synchronized with the reference signal associated with the first multiple clock at an early stage without malfunctions.
The clock recovery circuit in accordance with the fifteenth aspect of the present invention employs the DLL circuit for performing the delay synchronization process on the first multiple clock and the first delayed multiple clock to reduce the time required for synchronization, thereby providing the first to Nth recovered clocks from the outputs of the first to Nth logical OR means at an early stage. Further, since the variable delay element should provide the time delay of n times the period of the clock, the range of the frequency of the clock for synchronization is widely extended.
The clock recovery circuit in accordance with the sixteenth aspect of the present invention employs the PLL circuit for performing the phase synchronization process on the system clock and the oscillation signal. Since the system clock serving as the reference signal is independent of the first to Nth multiple clocks and is not multiplexed with the frame pulse signals, the PLL circuit may perform the phase synchronization process without malfunctions, and the outputs of the first to Nth logical OR means may provide the highly stable first to Nth recovered clocks at an early stage.
The fixed value detecting means of each of the first to Nth frame pulse signal separation circuits in accordance with the seventeenth aspect of the present invention outputs the ith recovered frame pulse signal (i=1 to N) which is active when the ith multiple clock maintains the fixed value for the ith period.
Therefore, the fixed value detecting means may be of a relatively simple construction by employing latch means for latching the value of the ith multiple clock when the ith clock does not have the fixed value for each predetermined period on the basis of the regularity of the ith recovered clock and the ith clock.
In the digital data transmission system in accordance with the eighteenth aspect of the present invention, the first clock multiplexing circuit of the first transmitting and receiving portion has the enabling function of forcing the first clock to be outputted intactly as the first multiple clock when the first synchronization detection signal indicates the unlocked state, and of multiplexing the first frame pulse signal with the first clock to output the first multiple clock when the first synchronization detection signal indicates the locked state. The second clock multiplexing circuit of the second transmitting and receiving portion has the enabling function of forcing the second clock to be outputted intactly as the second multiple clock when the second synchronization detection signal indicates the unlocked state, and of multiplexing the second frame pulse signal with the second clock to output the second multiple clock when the second synchronization detection signal indicates the locked state.
Since the first and second clocks have the same period, the first and second synchronization loop circuits require substantially the same time to synchronize the first and second reference signals associated with the second and first clocks and the first and second comparison output signals to change to the locked state.
Thus, the first clock multiplexing circuit of the first transmitting and receiving portion may output the first clock as the first multiple clock on the basis of the first synchronization detection signal provided therein until the locked state of the second synchronization loop circuit of the second transmitting and receiving portion is estimated. Therefore, the second synchronization loop circuit of the second clock recovery circuit of the second transmitting and receiving portion may be locked at an early stage without malfunctions.
Likewise, the second clock multiplexing circuit of the second transmitting and receiving portion may output the second clock as the second multiple clock on the basis of the second synchronization detection signal provided therein until the locked state of the first synchronization loop circuit of the first transmitting and receiving portion is estimated. Therefore, the first synchronization loop circuit of the first clock recovery circuit of the first transmitting and receiving portion may be locked at an early stage without malfunctions.
Additionally, the first and second clock multiplexing circuits change the contents of the first and second multiple clocks on the basis of the first and second synchronization detection signals provided therein, requiring the addition of no external signal lines for transmitting and receiving a signal to and from the exterior.
It is therefore an object of the present invention to provide a digital data transmission system which is capable of transmitting digital data, a frame pulse signal, and a clock using a required minimum number of signal lines and with a simple circuit structure.